Insights into the reliability of Ni/Cu plated p-PERC silicon solar cells

Selective laser ablation of dielectric layers in combination with plated Ni/Cu/Ag contacts have been investigated by many photovoltaic researchers. Despite that there has been quite some practical progress on improved processing, the reliability of plated Ni/Cu/Ag cells still needs further insight and understanding. In this paper, the impact of laser induced defects that result from a ps-laser (wavelength 355nm) ablation on the performance of p-type PERC cells has been studied. A thermal stress experiment at 235 degrees C is applied. It is shown that the defects formed during the laser ablation process do indeed decrease the cell performance. A higher laser fluence results in lower fill factor and therefore lower efficiency. Moreover, the cells with higher laser fluence ablation degrade faster compared to the cells which had lower laser fluence to open the dielectric layer. The second part of the paper focuses on characterization of the p-n junction of the laser ablated cells by Deep Level Transient Spectroscopy (DLTS) before and after thermal ageing. A hole trap around 80K was found for all samples, which is related to point defects induced during the cell processing. A broad peak around 200K observed for the ablated cells with high laser fluence could correspond to dislocations induced by the laser ablation. This peak is shifted to higher energy (closer to the silicon mid-gap) after annealing, which may be due to impurity decoration during the annealing

Scale up of advanced packaging and system integration for hybrid technologies

This paper presents an overview of challenges in system integration for 2.5D/3D assemblies, including copackaged optics and electronics, MEMS and microfluidics. It addresses the gap between early-stage prototypes and volume manufacturing that need true advanced packaging and system integration to realize their complex multi-technology devices. This is done by means of a virtual demonstrator that include both 2.5D/3D assemblies of ASICs and integrated photonic devices, as well as MEMS and microfluidics devices. It also addresses lowering the cost barrier for users accessing these technologies for their products, such that it will enable an increased uptake of system integration by the industry at large

Mechanical and physical behaviour of intermetallics in leadfree flip chip interconnections

In dit werk wordt het gebruik van zuiver Sn als loodvrij alternatief voor soldeer flip chip toepassingen onderzocht. De reactie van Sn met verschillende onderliggende soldeerbare metaallagen (Cu, Ni of Co) werd bestudeerd. Het gebruik van Co als soldeerbare metaallaag is eerder uitzonderlijk en uniek voor dit werk. Deze lagen vormen intermetallische verbindingen met Sn waardoor er een goede hechting wordt gegarandeerd. Anderzijds vormen deze verbindingen, omwille van hun bros karakter, een risico voor de mechanische stabiliteit van de connectie. Het gedrag van verschillende metaallaag – Sn combinaties werd onderling vergeleken voor verschillende betrouwbaarheidstesten. Deze testen simuleren de condities die in de praktijk voorkomen waardoor er eveneens een schatting kon gemaakt worden van de levensduur. Verouderingstesten werden uitgevoerd en de interdiffusiecoëfficiënten en activatie-energie waarden werden opgemeten (hoofdstuk 3). Rekening houdend met de stoechiometrie en de verhoudingen van de gevormde intermetallische fazes werd hiermee, voor een specifiek thermisch budget, niet alleen de aangroei van de intermetallische faze voorspeld maar ook de consumptie van de onderliggende metaallaag berekend. Tijdens reflow (smelten van Sn) is er een veel grotere metaallaag consumptie bij Cu dan bij Ni. Voor veroudering op hoge temperatuur (150-175oC) werd er eveneens een snellere consumptie vastgesteld voor Cu. Alleen voor het lage temperatuursgebied (100-125oC) werden gelijkaardige interdiffusiecoefficienten gevonden voor beide metaallagen. Het diffusiegedrag wordt echter grondig veranderd wanneer er ook een elektrische stroom door de soldeerverbinding wordt aangelegd. De invloed van een elektrische stroom op de stabiliteit van de metaallaag en intermetallische faze werd onderzocht (hoofdstuk 4). Hiervoor werd een bijzondere test structuur ontwikkeld die het mogelijk maakt om de verschillende contacten van een soldeerverbinding afzonderlijk elektrisch op te meten. Er werd aangetoond dat het verbreken van het elektrisch contact altijd optreedt aan de kathodische zijde van de soldeerverbinding. Voor een breed gebied van test condities (temperatuur tussen 100 en 175oC en stroomdichtheid tussen 0.05 en 0.16mA/m2) was de algemene trend dat Cu metaallagen sneller falen. Er werden verschillende falingsmechanismes vastgesteld voor beide metaallagen: in het geval van Cu gebeurt faling door consumptie van de metaallaag en in het geval van Ni, door de vorming van Kirkendall holtes tussen het Sn en de Ni3Sn4 intermetallische laag. Hierdoor kan de levensduur van de Cu metaallaag verlengd worden wanneer deze laag dikker gemaakt wordt. Tenslotte werden de flip chip assemblages thermisch gecycleerd om hun mechanisch gedrag te karakteriseren (hoofdstuk 5). Zowel voor de Sn als de Sn-Pb referentie monsters werd vermoeiing met scheurgroei door het soldeer vastgesteld. De levensduur van Sn verbindingen kon drastisch verlengd worden door het gebruik van Co als chip metallisatie. Uit deze testen blijkt dat niet zozeer de omschakeling naar Sn als loodvrij alternatief een probleem vormt, maar dat vooral het kleiner worden van de connecties, de betrouwbaarheid van de soldeerverbindingen in het gedrang zal brengen. Hierdoor wordt de verhouding van de dikte van de intermetallische laag tot het resterende soldeer alsmaar groter waardoor het gedrag van deze lagen belangrijker wordt. Uiteindelijk leidt miniaturisatie tot flip chip verbindingen die volledig uit een intermetallische faze zijn opgebouwd (hoofdstuk 6).status: publishe

Solid state diffusion in Cu-Sn and Ni-Sn diffusion couples with flip-chip scale dimensions

The formation and growth rate of intermetallics of frequently used metallisation systems for flip-chip bumping have been studied and are reported for many years. However, no data are available on diffusion couples with flip-chip processing methods and actual flip-chip scale dimensions. In this paper, the interdiffusion coefficients and activation energies of Cu-Sn and Ni-Sn intermetallic formations are measured on flip-chip bumps with 40 µm bond pad diameter. Also the morphology of the metallurgical reactions is described. Furthermore, the ideal case of a binary diffusion system is seldom present in real-life. In practice, the presence of additional alloying elements has an impact on the intermetallic stoichiometry and even on intermetallic growth and morphology. It is shown that small quantities of Cu in a Ni-Sn system can have a beneficial effect on the Ni consumption but larger quantities result in extreme scalloping of the intermetallic interface.status: publishe

Electrically active defects in plated crystalline silicon n⁺p solar cells : a DLTS perspective

Laser ablation (LA) has been compared with standard wet etching for contact opening in crystalline silicon n(+)p solar cells, from a perspective of electrically active defects, assessed by Deep-Level Transient Spectroscopy (DLTS). Copper metallization is employed, including a plated nickel diffusion barrier. It is shown that a hole trap around 0.17 eV above the valence band is systematically present in the depletion region of the junctions, irrespective of the contact opening method. It is believed that this could correspond with the substitutional nickel donor level in silicon and indicates that nickel in-diffusion occurs during the contact processing. No clear evidence for the presence of electrically active copper has been found. In addition, two other hole traps H2 and H3, belonging to point defects, have been observed after wet etching and standard LA, while for the highest laser power (hard LA) a broad band develops around 175 K, which is believed to be associated with laser-ablation-induced dislocations, penetrating the p-type base region. Evidence will also be given for the impurity decoration of the dislocations, which enhances their electrical activity

Influence of intermetallic properties on reliability of lead-free flip-chip solder joints

Electroplated pure tin bumping as a lead-free alternative for ultra fine pitch applications is a relatively easy process and has provided us with comparable results to eutectic Sn/Pb for thermal cycling reliability. Experimentally, it has been reported that a significantly higher (~40%) thermal cycle fatigue life is seen with the use of cobalt under bump metallization (UBM) instead of copper UBM for a flip-chip device assembled on an alumina substrate. In the current approaches used to estimate fatigue life of solder joints, the solder joint is treated as a homogenous material and modeled as such. However, the smaller joint sizes and higher reactivity of Sn implies that a larger amount of intermetallics are formed as a percentage of bump volume. The existing approach cannot account for the influence on the fatigue behavior of these intermetallic layers within the solder joint. In order to investigate if a simplified engineering approach can provide some insight into this issue, we have attempted to explicitly model the intermetallics as a continuous but separate part of the solder joint. The main damage parameter investigated is the accumulated inelastic strain in a single thermal cycle. From the results, it is clear that the Young's modulus of the intermetallic layer plays an important role, more so when the ratio of intermetallic thickness to the solder joint standoff increases. Thickness of the intermetallic layer also influences the overall strain accumulation in the same manner. The CTE of the intermetallic layer has a relatively lesser influence on the strain accumulation. Both the experimental and FE results suggest that changing the UBM from copper to cobalt can improve the fatigue life by 20%-30%.status: publishe

Creep behavior of mixed SAC 405/SnPb soldered assemblies in shear loading

In this work, the creep behavior of mixed lead free (Sn4%Ag 0.5%Cu) (SAC 405) and eutectic tin lead (Sn37%Pb) solders has been studied. A double lap shear configuration was used to study the creep response of the mixed solder joints, the dimensions of which ranged from 300 to 500 μm. The tested solder specimens were wafer level chip scale packages (WLCSP) bumped with preformed solder spheres. The volume ratios of the two solders were controlled by using preformed solders spheres in the size range of 300 to 450 μm. All the specimens were reflowed at a profile with 260°C peak temperature resulting in a complete mixing of the two solder alloys. The creep tests were done at constant stress levels by applying a constant load to the specimen. The displacement of the joints was recorded as a function of time from which the steady state strain rates were determined. In the present experiments, these ranged from 1E-3/s to 1E-9/s. while the applied stress levels ranged from 5 MPa to 40 MPa. The tests were repeated for 3 different temperatures: 40°C, 70°C and 100°C The stress - strain rate data seems to fit well to the SINH creep model and the obstacle controlled model. The fitting to the power law shows different slopes above and below 10 MPa stress levels. In addition, the effect of isothermal aging at 125 °C on the creep behavior was also studied. In general, the mixed solder joints creep faster than SAC 405 and their deformation rate lies in between that of the eutectic SnPb and SAC 405 solders. © 2007 IEEE.status: publishe